JOINT(S)
has strong hardware design expertise in the areas of IC design
and services provided by us are designed to suit the peak
and general time requirement of silicon manufacturers at different
stages on the life cycle from design conceptualization to
final tape out:-
• Modeling and conceptualization of product based on
specifications.
• Circuit design and functional verification for Memories
and Standard cells.
• Layout design and verification for memories and Standard
cells.
• Layout design for Analog cells (IO).
• Post Layout Characterization services for all full
custom cells.
• Characterization services for IO (Generating synopsys
models).
• Place and Route services (Chip Layout).
• Place and Route services for test chip of memories.
• Q&A services in Memories, Standard cells and other
designs.
• CAD services.
We
have trained man power for tools provided by all major EDA
vendors like Cadence , Synopsys , Magma , Genesys etc
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