We have openings in the field of Design for those who
aspire to achieve ,have sound technical knowledge and
necessarily acquired a degree in Electronics and
Communication.

                  
                  Should have hands-on experience in Physical Design
                  
and Verification activities like 
– Timing driven synthesis,
– Floor Planning,
– Timing driven Placement and Routing,
– ECO, 
– Signal Integrity/Crosstalk analysis,
- Circuit design for Standard cells and memories.
- Layout Design ( Analog and Digital),
– IR Drop Analysis, DRC, LVS, Timing Closure. etc.

• Should have good knowledge of methodology and
experience with one or more 
EDA tool flow
– Cadence! , 
– Magma, 
– Synopsys. 
• Should have done Physical design for two or more
large complex ASIC/SoC. 

Desirable Skills:

• Hands-on experience in Package design 
– Flip chip,
– Ball Placement etc. 

• Interface with Front end design team 


If the above skill set matches to your profile, You
are invited to send out your resume to us at
contactus@jointschip.com and for furthur information you
can write to us at contactus@jointschip.com